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a
FEATURES
Low-Power Analog Front End with DSP Microcomputer AD73411
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN CONTROL DATA ADDRESS GENERATORS DAG 1 DAG 2 MEMORY 16K PM 16K DM
(OPTIONAL (OPTIONAL 8K) 8K)
AFE PERFORMANCE 16-Bit A/D Converter 16-Bit D/A Converter Programmable Input/Output Sample Rates 76 dB ADC SNR 77 dB DAC SNR 64 kS/s Maximum Sample Rate -90 dB Crosstalk Low Group Delay (25 s Typ per ADC Channel, 50 s Typ per DAC Channel) Programmable Input/Output Gain On-Chip Reference DSP PERFORMANCE 19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS Sustained Performance AD73411-80 80K Bytes of On-Chip RAM, Configured as 16K Words Program Memory RAM and 16K Words Data Memory RAM AD73411-40 40K Bytes of On-Chip RAM, Configured as 8K Words Program Memory RAM and 8K Words Data Memory RAM
FULL MEMORY MODE PROGRAMMABLE I/O AND FLAGS EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER OR EXTERNAL DATA BUS TIMER INTERNAL DMA PORT HOST MODE
PROGRAM SEQUENCER
PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS
PROGRAM MEMORY DATA DATA MEMORY DATA
ARITHMETIC UNITS ALU MAC SHIFTER ADSP-2100 BASE ARCHITECTURE
SERIAL PORTS SPORT 0 SPORT 1
REF
SERIAL PORT SPORT 2
ADC
DAC
ANALOG FRONT END SECTION
GENERAL DESCRIPTION
The AD73411 is a single device incorporating a single analog front end (AFE) and a microcomputer optimized for digital signal processing (DSP) and other high-speed numeric processing applications. The AD73411's analog front end (AFE) section is suitable for general-purpose applications including speech and telephony. The AFE section features a 16-bit A/D converter and a 16-bit D/A converter. Each converter provides 76 dB signal-to-noise ratio over a voiceband signal bandwidth. The AD73411 is particularly suitable for a variety of applications in the speech and telephony area, including low bit rate, highquality compression, speech enhancement, recognition, and synthesis. The low group delay characteristic of the AFE makes it suitable for single or multichannel active control applications. The A/D and D/A conversion channels feature programmable input/output gains with ranges of 38 dB and 21 dB respectively. An on-chip reference voltage is included to allow single supply operation. REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
The sampling rate of the AFE is programmable with four separate settings offering 64, 32, 16, and 8 kHz sampling rates (from a master clock of 16.384 MHz) while the serial port (SPORT2) allows easy expansion of the number of I/O channels by cascading extra AFEs external to the AD73411. The AD73411's DSP engine combines the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The AD73411-80 integrates 80K bytes of on-chip memory configured as 16K words (24-bit) of program RAM, and 16K words (16-bit) of data RAM. The AD73411-40 integrates 40K bytes of on-chip memory configured as 8K words (24bit) of program RAM, and 8K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The AD73411 is available in a 119-ball PBGA package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD73411-SPECIFICATIONS1
Parameter AFE SECTION REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Min 1.08
(AVDD = DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, fMCLK = 16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)
Typ Max Unit Test Conditions/Comments
1.2 50 145
1.32
V ppm/C
0.1 F Capacitor Required from REFCAP to AGND2
Absolute Voltage, VREFOUT
ADC SPECIFICATIONS Maximum Input Range at VIN 2, 3 Nominal Reference Level at VIN (0 dBm0) Absolute Gain PGA = 0 dB PGA = 38 dB Gain Tracking Error Signal to (Noise + Distortion) PGA = 0 dB
1.08
1.2
1.578 -2.85 1.0954 -6.02
1.32
V
V p-p dBm V p-p dBm
Unloaded
Measured Differentially Max Input = (1.578/1.2) x VREFCAP Measured Differentially
-2.2
-0.6 -1.0 0.1 76 74 72 56 60 59 -85 -85 -82 -76 -100
+1.0
dB dB dB dB dB dB dB dB dB
71 70
PGA = 38 dB Total Harmonic Distortion PGA = 0 dB PGA = 38 dB Intermodulation Distortion Idle Channel Noise Crosstalk DC Offset Power Supply Rejection Group Delay4, 5 Input Resistance at PGA 2, 4, 6 DAC SPECIFICATIONS Maximum Voltage Output Swing 2 Single-Ended Differential Nominal Voltage Output Swing (0 dBm0) Single-Ended Differential Output Bias Voltage4 Absolute Gain Gain Tracking Error Signal to (Noise + Distortion) PGA = 0 dB PGA = 6 dB Total Harmonic Distortion at 0 dBm0 PGA = 0 dB PGA = 6 dB Intermodulation Distortion Idle Channel Noise Crosstalk 1.08 -1.8 -20
1.0 kHz, 0 dBm0 1.0 kHz, 0 dBm0 1.0 kHz, +3 dBm0 to -50 dBm0 Refer to Figure ? 300 Hz to 3400 Hz; 0 Hz to fSAMP/2 300 Hz to 3400 Hz; fSAMP = 64 kHz 0 Hz to fSAMP/2; fSAMP = 64 kHz 300 Hz to 3400 Hz; 0 Hz to fSAMP/2 300 Hz to 3400 Hz 300 Hz to 3400 Hz PGA = 0 dB PGA = 0 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0 DAC Input at Idle PGA = 0 dB Input Signal Level at AVDD and DVDD Pins 1.0 kHz, 100 mV p-p Sine Wave fSAMP = 64 kHz DMCLK = 16.384 MHz
-75
dB dB dB dBm0 dB mV dB s k
+2 -84 25 45
+25
1.578 -2.85 3.156 3.17 1.0954 -6.02 2.1909 0 1.2 -0.7 0.1 77 76 77 77 -80 -80 -76 -82 -100 -70
V p-p dBm V p-p dBm V p-p dBm V p-p dBm V dB dB dB dB dB dB dB dB dB dBm0 dB
PGA = 6 dB Max Output = (1.578/1.2) x VREFCAP PGA = 6 dB Max Output = 2 x ((1.578/1.2) x VREFCAP PGA = 6 dB PGA = 6 dB REFOUT Unloaded 1.0 kHz, 0 dBm0; Unloaded 1.0 kHz, +3 dBm0 to -50 dBm0 300 Hz to 3400 Hz 300 Hz to 3400 Hz; fSAMP = 64 kHz 300 Hz to 3400 Hz 300 Hz to 3400 Hz; fSAMP = 64 kHz
1.32 +0.4
70
PGA = 0 dB PGA = 0 dB ADC Input Signal Level: AGND; DAC Output Signal Level: 1.0 kHz, 0 dBm0
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AD73411
Parameter DAC SPECIFICATIONS (Continued) Power Supply Rejection Group Delay4, 5 Min Typ -81 25 50 Max Unit dB s s Test Conditions/Comments Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave fSAMP = 64 kHz; Interpolator Bypassed fSAMP = 64 kHz
Output DC Offset2, 7
LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage
-30
DVDD - 0.8 0
+5
+50
DVDD 0.8
mV
V V
PGA = 6 dB
IIH, Input Current LOGIC OUTPUT
VOH, Output High Voltage VOL, Output Low Voltage Three-State Leakage Current POWER SUPPLIES AVDD DVDD IDD9
-10
DVDD - 0.4 0 -10 3.0 3.0
+10
DVDD 0.4 +10 3.6 3.6
A
V V A V V See Table I |IOUT| 100 A |IOUT| 100 A
NOTES 1 Operating temperature range is as follows: -20C to +85C. Therefore, TMIN = -20C and TMAX = +85C. 2 Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted). 3 At input to sigma-delta modulator of ADC. 4 Guaranteed by design. 5 Overall group delay will be affected by the sample rate and the external digital filtering. 6 The ADC's input impedance is inversely proportional to DMCLK and is approximated by: (3.3 x 1011)/DMCLK. 7 Between VOUTP and VOUTN. 8 At VOUT output. 9 Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground, no load on analog outputs. Specifications subject to change without notice.
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AD73411-SPECIFICATIONS
Parameter DSP SECTION VIH VIH VIL VOH Hi-Level Input Voltage1, 2 Hi-Level CLKIN Voltage Lo-Level Input Voltage1, 3 Hi-Level Output Voltage1, 4, 5
(AVDD = DVDD = VDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, fMCLK = 16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)
Test Conditions @ VDD = max @ VDD = max @ VDD = min @ VDD = min IOH = -0.5 mA @ VDD = min IOH = -100 A6 @ VDD = min IOL = 2 mA @ VDD = max VIN = VDD max @ VDD = max VIN = 0 V @ VDD = max VIN = VDD max8 @ VDD = max VIN = 0 V8 @ VDD = 3.3 tCK = 19 ns10 tCK = 25 ns10 tCK = 30 ns10 @ VDD = 3.3 TAMB = 25C tCK = 19 ns10 tCK = 25 ns10 tCK = 30 ns10 @ VIN = 2.5 V fIN = 1.0 MHz TAMB = 25C @ VIN = 2.5 V fIN = 1.0 MHz TAMB = 25C Min 2.0 2.2 0.8 2.4 VDD - 0.3 0.4 10 10 10 10 12 11 10 Typ Max Unit V V V V V V A A A A mA mA mA
VOL IIH IIL IOZH IOZL IDD
Lo-Level Output Voltage1, 4, 5 Hi-Level Input Current3 Lo-Level Input Current3 Three-State Leakage Current7 Three-State Leakage Current7 Supply Current (Idle)9
IDD
Supply Current (Dynamic)11
45 43 36
mA mA mA
CI CO
Input Pin Capacitance3, 6, 12 Output Pin Capacitance6, 7, 12, 13
8
pF
8
pF
NOTES 1 Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7. 2 Input only pins: RESET, BR, DR0, DR1, PWD. 3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH. 5 Although specified for TTL outputs, all AD73411 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads. 6 Guaranteed but not tested. 7 Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0-PF7. 8 0 V on BR. 9 Idle refers to AD73411 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND. 10 VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section. 11 IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and Type 6, and 20% are idle instructions. 12 Applies to PBGA package type. 13 Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice.
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AD73411 POWER CONSUMPTION
Parameter AFE SECTION ADC Only On ADC and DAC On REFCAP Only On REFCAP and REFOUT Only On All AFE Sections Off All AFE Sections Off DSP SECTION Idle Mode Dynamic Typ 7 11 0.65 2.7 0.6 5 A 6.4 43 Max 8 12.5 1.00 3.8 0.75 30 A SE 1 1 0 0 0 0 MCLK On Yes Yes No No Yes No Test Conditions REFOUT Disabled REFOUT Disabled REFOUT Disabled
MCLK Active Levels Equal to 0 V and DVDD Digital Inputs Static and Equal to 0 V or DVDD
NOTES The above values are in mA and are typical values unless otherwise noted. Specifications subject to change without notice.
TIMING CHARACTERISTICS-AFE SECTION
Parameter Clock Signals t1 t2 t3 Serial Port t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Limit 61 24.4 24.4 t1 0.4 x t1 0.4 x t1 20 0 10 10 10 10 30 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns max ns max Description See Figure 1 16.384 MHz AMCLK Period MCLK Width High MCLK Width Low See Figures ? and ? SCLK Period (SCLK = AMCLK) SCLK Width High SCLK Width Low SDI/SDIFS Setup Before SCLK Low SDI/SDIFS Hold After SCLK Low SDOFS Delay from SCLK High SDOFS Hold After SCLK High SDO Hold After SCLK High SDO Delay from SCLK High SCLK Delay from MCLK
Specifications subject to change without notice.
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AD73411
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . . -0.3 V to +4.6 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . -0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND . . . . . -0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -20C to +85C Storage Temperature Range . . . . . . . . . . . . -40C to +125C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C PBGA, JA Thermal Impedance . . . . . . . . . . . . . . . . . 25C/W
Reflow Soldering Maximum Temperature . . . . . . . . . . . . . . . . . . . . . . . 225C Time at Maximum Temperature . . . . . . . . . . . . . . . . . 15 sec Maximum Temperature Ramp Rate . . . . . . . . . . . . 1.3C/sec
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD73411BB-80 AD73411BB-40
Temperature Range -20C to +85C -20C to +85C
Package Description 119-Ball Plastic Ball Grid Array 119-Ball Plastic Ball Grid Array
Package Option B-119 B-119
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD73411 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PBGA BALL CONFIGURATION
1 A B C D E F G H J K L M N P R T U
IRQE/PF4 IRQL0/PF5 IRQL1/PF6 IRQ2/PF7 DT0 DR0 TFS1/IRQ1 SCLK1 EMS ELOUT BG EBG BR EBR SDO VINP AGND
2
DMS PMS IOMS CMS TFS0 SCLK0 RFS1/IRQ0 ERESET EE ELIN D3/IACK D2/IAD15 D1/IAD14 D0/IAD13 SDOFS NC AVDD
3
VDD (INT) WR RD BMS RFS0 DT1/F0 DR1/FI RESET ECLK EINT D5/IAL D4/IS VDD (INT) DVDD SDIFS VINN NC
4
CLKIN XTAL VDD (EXT) CLKOUT A3/IAD2 PWDACK GND PF3 D23 D19 D8 D7/IWR D6/IRD DGND SDI NC NC
5
A11/IAD10 A12/IAD11 A13/IAD12 GND A2/IAD1 BGH PWD FL0 D22 D18 D9 VDD (EXT) GND ARESET SE NC VOUTP
6
A7/IAD6 A8/IAD7 A9/IAD8 A10/IAD9 A1/IAD0
7
A4/IAD3 A5/IAD4 GND A6/IAD5 A0
MODE A /PF0 MODE B/PF1 VDD (EXT) FL1 D21 D17 D12 D11 D10 SCLK2 REFCAP NC VOUTN MODE C /PF2 FL2 D20 D16 D15 D14 D13 AMCLK REFOUT NC NC
TOP VIEW NOTES: VDD (INT) - DSP CORE SUPPLY VDD (EXT) - DSP I/O DRIVER SUPPLY BOTH VDD (INT) AND VDD (EXT) SHOULD BE POWERED FROM THE SAME SUPPLY.
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PBGA BALL FUNCTION DESCRIPTIONS Mnemonic VINP VINN REFOUT REFCAP DGND DVDD ARESET SCLK2 BGA Location T1 T3 R7 R6 P4 P3 P5 P6 Function This pin allows direct access to the positive input of the sigma-delta modulator. This pin allows direct access to the negative input of the sigma-delta modulator. Buffered Reference Output, which has a nominal value of 1.2 V. A Bypass Capacitor to AGND of 0.1 F is required for the on-chip reference. The capacitor should be fixed to this pin. AFE Digital Ground/Substrate Connection. AFE Digital Power Supply Connection. Active Low Reset Signal. This input resets the entire analog front end, resetting the control registers and clearing the digital circuitry. Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock data or control information to and from the serial port (SPORT2). The frequency of SCLK is equal to the frequency of the master clock (AMCLK) divided by an integer number--this integer number being the product of the external master clock rate divider and the serial clock rate divider. AFE Master Clock Input. AMCLK is driven from an external clock signal. If it is required to run the DSP and AFE sections from a common clock crystal, AMCLK should be connected to the XTAL pin of the DSP section. Serial Data Output of the Codec. Both data and control information may be output on this pin and is clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low. Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in three-state when SE is low. Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low. Serial Data Input of the Codec. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low. SPORT2 Enable. Asynchronous input enable pin for SPORT2. When SE is set low by the DSP, the output pins of SPORT2 are three-stated and the input pins are ignored. SCLK2 is also disabled internally in order to decrease power dissipation. When SE is brought high, the control and data registers of SPORT2 are at their original values (before SE was brought low), however the timing counters and other internal registers are at their reset values. AFE Analog Ground/Substrate Connection. AFE Analog Power Supply Connection. Analog Output from the Positive Terminal of the Output. Analog Output from the Negative Terminal of the Output. (Input) Processor Reset Input. (Input) Bus Request Input. (Output) Bus Grant Output. (Output) Bus Grant Hung Output. (Output) Data Memory Select Output. (Output) Program Memory Select Output. (Output) Memory Select Output. (Output) Byte Memory Select Output. (Output) Combined Memory Select Output. (Output) Memory Read Enable Output. (Output) Memory Write Enable Output. (Input) Edge- or Level-Sensitive Interrupt Request 1. (Input/Output) Programmable I/O Pin. (Input) Level-Sensitive Interrupt Requests 1. (Input/Output) Programmable I/O Pin.
AMCLK
P7
SDO SDOFS
R1 R2
SDIFS
R3
SDI SE
R4 R5
AGND AVDD VOUTP VOUTN RESET BR BG BGH DMS PMS IOMS BMS CMS RD WR IRQ2/ PF7 IRQL1/ PF6
U1 U2 U5 U6 H3 N1 L1 F5 A2 B2 C2 D3 D2 C3 B3 D1 C1
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AD73411
PBGA BALL FUNCTION DESCRIPTIONS (Continued) Mnemonic IRQL0/ PF5 IRQE/ PF4 PF3 Mode C/ PF2 Mode B/ PF1 Mode A/ PF0 CLKIN XTAL CLKOUT SPORT0 TFS0 RFS0 DT0 DR0 SCLK0 SPORT1 TFS1/ IRQ1 RFS1 IRQ0 DT1/ FO DR1/ FI SCLK1 FL0 FL1 FL2 VDD(INT) VDD(EXT) GND BGA Location B1 A1 H4 G7 F7 F6 A4 B4 D4 E2 E3 E1 F1 F2 G1 G2 F3 G3 H1 H5 H6 H7 A3 N3 C4 G6 M5 C7 D5 G4 N5 H2 J1 J2 J3 K1 K2 K3 P1 M1 A0-E7; A1/IAD0-E6; A2/IAD1-E5; A3/IAD2-E4; A4/IAD3-A7; A5/IAD4-B7; A6/IAD5-D7; A7/IAD6-A6; A8/IAD7-B6; A9/IAD8-C6; A10/IAD9-D6; A11/IAD10-A5; A12/IAD11-B5; A13/IAD12-C5 D0/IAD13-P2; D1/IAD14-N2; D2/IAD15-M2; D3/IACK-L2; D4/IS-M3; D5/IAL-L3; D6/IRD-N4; D7/IWR-M4; D8-L4; D9-L5; D10-N6; D11-M6; D12-L6; D13-N7; D14-M7; D15-L7; D16-K7; D17-K6; D18-K5; D19-K4; D20-J7; D21-J6; D22-J5; D23-J4 Function (Input) Level-Sensitive Interrupt Requests 1. (Input/Output) Programmable I/O Pin. (Input) Edge-Sensitive Interrupt Requests 1. (Input/Output) Programmable I/O Pin. (Input/Output) Programmable I/O Pin During Normal Operation. (Input) Mode Select Input--Checked Only During RESET. (Input/Output) Programmable I/O Pin During Normal Operation. (Input) Mode Select Input--Checked Only During RESET. (Input/Output) Programmable I/O Pin During Normal Operation. (Input) Mode Select Input--Checked Only During RESET. (Input/Output) Programmable I/O Pin During Normal Operation. (Inputs) Clock or Quartz Crystal Input. The CLKIN input cannot be halted or changed during operation nor operated below 10 MHz during normal operation. (Output) Processor Clock Output. (Input/Output) SPORT0 Transmit Frame Sync. (Input/Output) SPORT0 Receive Frame Sync. (Output) SPORT0 Transmit Data. (Input) SPORT0 Receive Data. (Input/Output) SPORT0 Serial Clock. (Input/Output) SPORT1 Transmit Frame Sync. (Input) Edge or Level Sensitive Interrupt. (Input/Output) SPORT1 Receive Frame Sync. (Input) Edge or Level Sensitive Interrupt. (Output) SPORT1 Transmit Data. (Output) Flag Out2. (Input) SPORT1 Receive Data. (Input) Flag In2. (Input/Output) SPORT1 Serial Clock. (Output) Flag 0. (Output) Flag 1. (Output) Flag 2. (Input) DSP Core Supply. (Input) DSP I/O Interface Supply. DSP Ground.
EZ-ICE Port ERESET EMS EE ECLK ELOUT ELIN EINT EBR EBG
Address Bus
Data Bus
NOTES 1 Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 2 SPORT configuration determined by the DSP System Control Register. Software configurable.
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AD73411
ARCHITECTURE OVERVIEW
The AD73411 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The AD73411 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.
POWER-DOWN CONTROL DATA ADDRESS GENERATORS DAG 1 DAG 2 MEMORY 16K PM 16K DM
(OPTIONAL (OPTIONAL 8K) 8K)
FULL MEMORY MODE PROGRAMMABLE I/O AND FLAGS EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER OR EXTERNAL DATA BUS TIMER INTERNAL DMA PORT HOST MODE
PROGRAM SEQUENCER
PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS
PROGRAM MEMORY DATA DATA MEMORY DATA
ARITHMETIC UNITS ALU MAC SHIFTER ADSP-2100 BASE ARCHITECTURE
SERIAL PORTS SPORT 0 SPORT 1
REF
SERIAL PORT SPORT 2
ADC
DAC
ANALOG FRONT END SECTION
Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. An interface to low-cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. The AD73411 can respond to eleven interrupts. There can be up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable), and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. The AD73411 provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs and three flags are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD).
Analog Front End
Figure 1. Functional Block Diagram
Figure 1 is an overall block diagram of the AD73411. The processor section contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units directly process 16-bit data and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the AD73411 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops.
The AFE section is configured as a separate block that is normally connected to either SPORT0 or SPORT1 of the DSP section. As it is not hardwired to either SPORT, users have total flexibility in how they wish to allocate system resources to support the AFE. It is also possible to further expand the number of analog I/O channels connected to the SPORT by cascading other single or dual channel AFEs (AD73311 or AD73322) external to the AD73411.
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AD73411
AVDD1 AVDD2 DVDD VINP ANALOG LOOPBACK/ SINGLE-ENDED ENABLE SDI 0/38dB PGA ANALOG SIGMA-DELTA MODULATOR DECIMATOR SDIFS SCLK SERIAL I/O PORT VOUTP +6/-15dB PGA VOUTN REFCAP REFOUT REFERENCE CONTINUOUS TIME LOW-PASS FILTER SWITCHEDCAPACITOR LOW-PASS FILTER 1-BIT DAC DIGITAL SIGMA-DELTA MODULATOR SDO SDOFS SE MCLK RESET
VINN
INTERPOLATOR
AD73411
AGND1
AGND2
DGND
Figure 2. Functional Block Diagram of Analog Front End Section
The AFE is configured as a single I/O channel (similar to that of the discrete AD73311L; refer to the AD73311L data sheet for more details) having a 16-bit sigma-delta-based ADC and DAC. Both ADC and DAC share a common reference whose nominal value is 1.2 V. Figure 2 shows a block diagram of the AFE section of the AD73411. It shows an ADC and DAC as well as a common reference. Communication to both channels is handled by the SPORT2 block which interfaces to either SPORT0 or SPORT1 of the DSP section. The I/O channel features fully differential inputs and outputs. The input section allows direct connection to the internal Programmable Gain Amplifier at the input of the sigma-delta ADC section. The input section also features programmable differential channel inversion and configuration of the differential input as two separate single-ended inputs. The ADC features a second order sigma-delta modulator which samples at MCLK/8. Its bitstream output is filtered and decimated by a Sinc-cubed decimator to provide a sample rate selectable from 64 kHz, 32 kHz, 16 kHz or 8 kHz (based on an MCLK of 16.384 MHz). The DAC channel features a Sinc-cubed interpolator which increases the sample rate from the selected rate to the digital sigma-delta modulator rate of MCLK/8. The digital sigma-delta modulator's output bitstream is fed to a single-bit DAC whose output is reconstructed/filtered by two stages of low-pass filtering (switched capacitor and continuous time) before being applied to the differential output driver.
FUNCTIONAL DESCRIPTION Encoder Channel
or from the DAC output via the Analog Loop-Back (ALB) arrangement. Differential inputs can be inverted and it is also possible to use the device in single-ended mode, which allows the option of using the VINP, VINN pins as two separate single-ended inputs, either of which can be selected under software control.
Programmable Gain Amplifier
The encoder section's analog front end comprises a switched capacitor PGA that also forms part of the sigma-delta modulator. The SC sampling frequency is DMCLK/8. The PGA, whose programmable gain settings are shown in Table I, may be used to increase the signal level applied to the ADC from low output sources such as microphones, and can be used to avoid placing external amplifiers in the circuit. The input signal level to the sigma-delta modulator should not exceed the maximum input voltage permitted. The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0-2) in Control Register D.
Table I. PGA Settings for the Encoder Channel
IGS2 0 0 0 0 1 1 1 1
ADC
IGS1 0 0 1 1 0 0 1 1
IGS0 0 1 0 1 0 1 0 1
Gain (dB) 0 6 12 18 20 26 32 38
The encoder channel consists of an input configuration block, a switched capacitor PGA and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which forms part of the sigma-delta ADC, also performs critical system-level filtering. Due to the high level of oversampling, the input antialias requirements are reduced such that a simple single pole RC stage is sufficient to give adequate attenuation in the band of interest.
Input Configuration Block
The input configuration block consists of a multiplexing arrangement that allows selection of various input configurations. This includes ADC input selection from either the VINP, VINN pins
The ADC consists of an analog sigma-delta modulator and a digital antialiasing decimation filter. The sigma-delta modulator noise-shapes the signal and produces 1-bit samples at a DMCLK/8 rate. This bitstream, representing the analog input signal, is input to the antialiasing decimation filter. The decimation filter reduces the sample rate and increases the resolution.
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Analog Sigma-Delta Modulator
The AD73411 input channel employs a sigma-delta conversion technique, which provides a high resolution 16-bit output with system filtering being implemented on-chip. Sigma-delta converters employ a technique known as oversampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD73411, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The main effect of oversampling is that the quantization noise is spread over a very wide bandwidth, up to fS/2 = DMCLK/16 (Figure 3a). This means that the noise in the band of interest is much reduced. Another complementary feature of sigma-delta converters is the use of a technique called noise-shaping. This technique has the effect of pushing the noise from the band of interest to an out-of-band position (Figure 3b). The combination of these techniques, followed by the application of a digital filter, sufficiently reduces the noise in band to ensure good dynamic performance from the part (Figure 3c).
multiple of DMCLK/256, which is the decimation filter update rate. The final detail in Figure 4d shows the application of a final antialias filter in the DSP engine. This has the advantage of being implemented according to the user's requirements and available MIPS. The filtering in Figures 4a through 4c is implemented in the AD73411.
FB = 4kHz
FSINIT = DMCLK/8
a. Analog Antialias Filter Transfer Function
SIGNAL TRANSFER FUNCTION
NOISE TRANSFER FUNCTION
FB = 4kHz
BAND OF INTEREST fS/2 DMCLK/16
FSINIT = DMCLK/8
b. Analog Sigma-Delta Modulator Transfer Function
a.
NOISE-SHAPING BAND OF INTEREST
FB = 4kHz FSINTER = DMCLK/256
fS/2 DMCLK/16
c. Digital Decimator Transfer Function
b.
DIGITAL FILTER
FB = 4kHz FSFINAL = 8kHz
BAND OF INTEREST fS/2 DMCLK/16
FSINTER = DMCLK/256
d. Final Filter LPF (HPF) Transfer Function Figure 4. AD73411 ADC Frequency Responses
Decimation Filter
c. Figure 3. Sigma-Delta Noise Reduction
Figure 4 shows the various stages of filtering that are employed in a typical AD73411 application. In Figure 4a we see the transfer function of the external analog antialias filter. Even though it is a single RC pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (DMCLK/8) that it takes care of any signals that could be aliased by the sampling frequency. This also shows the major difference between the initial oversampling rate and the bandwidth of interest. In Figure 4b, the signal and noise-shaping responses of the sigma-delta modulator are shown. The signal response provides further rejection of any high frequency signals while the noise-shaping will push the inherent quantization noise to an out-of-band position. The detail of Figure 4c shows the response of the digital decimation filter (Sinc-cubed response) with nulls every REV. 0
The digital filter used in the AD73411 carries out two important functions. Firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator and secondly, it decimates the high-frequency bitstream to a lower rate 15-bit word. The antialiasing decimation filter is a sinc-cubed digital filter that reduces the sampling rate from DMCLK/8 at the modulator to an output rate at the SPORT of DMCLK/M (where M depends on the sample rate setting--M = 256 @ 64 kHz; M = 512 @ 32 kHz, M = 1024 @ 16 kHz, M = 2048 @ 8 kHz), and increases the resolution from a single bit to 15 bits. Its Z transform is given as: [(1-Z-N)/(1-Z-1)]3 where N is determined by the sampling rate (N = 32 @ 64 kHz, N = 64 @ 32 kHz, N = 128 @ 16 kHz, N = 256 @ 8 kHz). This ensures a minimal group delay of 25 s at the 64 kHz sampling rate. -11-
AD73411
ADC Coding
The ADC coding scheme is in twos complement format (see Figure 5). The output words are formed by the decimation filter, which grows the word length from the single-bit output of the sigma-delta modulator to a 15-bit word, which is the 16-bit transfer being used as a flag bit to indicate either control or data in the frame.
VREF + (VREF 0.32875) VINN
The output of the interpolation filter is fed to the DAC's digital sigma-delta modulator, which converts the 16-bit data to 1-bit samples at a rate of DMCLK/8. The modulator noise-shapes the signal so that errors inherent to the process are minimized in the passband of the converter. The bitstream output of the sigma-delta modulator is fed to the single bit DAC where it is converted to an analog voltage.
Analog Smoothing Filter and PGA
ANALOG INPUT
VREF
VREF - (VREF
0.32875)
VINP
10...00
00...00
01...11
ADC CODE DIFFERENTIAL
The output of the single-bit DAC is sampled at DMCLK/8, therefore it is necessary to filter the output to reconstruct the low frequency signal. The decoder's analog smoothing filter consists of a continuous-time filter preceded by a third-order switched-capacitor filter. The continuous-time filter forms part of the output programmable gain amplifier (PGA). The PGA can be used to adjust the output signal level from -15 dB to +6 dB in 3 dB steps, as shown in Table II. The PGA gain is set by bits OGS0, OGS1 and OGS2 (CRD:4-6) in Control Register D.
Table II. PGA Settings for the Decoder Channel
VREF + (VREF
0.6575) VINN
OGS2 0 0 0 0 1 1 1 1
OGS1 0 0 1 1 0 0 1 1
OGS0 0 1 0 1 0 1 0 1
Gain (dB) 6 3 0 -3 -6 -9 -12 -15
ANALOG INPUT
VREF
VREF - (VREF
0.6575)
VINP 00...00 01...11
10...00
ADC CODE SINGLE-ENDED
Figure 5. ADC Transfer Function
Decoder Channel
The decoder channel consists of a digital interpolator, digital sigma-delta modulator, a single bit digital-to-analog converter (DAC), an analog smoothing filter and a programmable gain amplifier with differential output.
DAC Coding
Differential Output Amplifiers
The decoder has a differential analog output pair (VOUTP and VOUTN). The output channel can be muted by setting the MUTE bit (CRD:7) in Control Register D. The output signal is dc-biased to the codec's on-chip voltage reference.
Voltage Reference
The DAC coding scheme is in twos complement format with 0x7FFF being full-scale positive and 0x8000 being full-scale negative.
Interpolation Filter
The anti-imaging interpolation filter is a sinc-cubed digital filter which upsamples the 16-bit input words from the SPORT input rate of DMCLK/M (where M depends on the sample rate setting (M = 256 @ 64 kHz; M = 512 @ 32 kHz, M = 1024 @ 16 kHz, M = 2048 @ 8 kHz), to a rate of DMCLK/8 while filtering to attenuate images produced by the interpolation process. Its Z transform is given as: [(1-Z-N)/(1-Z-1)]3 where N is determined by the sampling rate (N = 32 @ 64 kHz, N = 64 @ 32 kHz, N = 128 @ 16 kHz, N = 256 @ 8 kHz). The DAC receives 16-bit samples from the host DSP processor at a rate of DMCLK/M. If the host processor fails to write a new value to the serial port, the existing (previous) data is read again. The data stream is filtered by the anti-imaging interpolation filter, but there is an option to bypass the interpolator for the minimum group delay configuration by setting the IBYP bit (CRE:5) of Control Register E. The interpolation filter has the same characteristics as the ADC's antialiasing decimation filter.
The AD73411 reference, REFCAP, is a bandgap reference that provides a low noise, temperature-compensated reference to the DAC and ADC. A buffered version of the reference is also made available on the REFOUT pin and can be used to bias other external analog circuitry. The reference has a default nominal value of 1.2 V. The reference output (REFOUT) can be enabled for biasing external circuitry by setting the RU bit (CRC:6) of CRC.
AFE Serial Port (SPORT2)
The AFE section communicates with the DSP section via its bidirectional synchronous serial port (SPORT2), which interfaces to either SPORT0 or SPORT1 of the DSP section. SPORT2 is used to transmit and receive digital data and control information. This allows other single or dual codec devices to be cascaded together (up to a limit of eight codec units). In both transmit and receive modes, data is transferred at the serial clock (SCLK2) rate with the MSB being transferred first. Communications between the AFE section and the DSP section must always be initiated by the AFE section (AFE is in master mode--DSP SPORT is in slave mode). This ensures that there is no collision between input data and output samples.
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SPORT2 Overview
SPORT2 is a flexible, full-duplex, synchronous serial port whose protocol has been designed to allow extra AFE devices (AD733xx series), up to a maximum of eight I/O channels, to be connected in cascade to a DSP SPORT (0 or 1). It has a very flexible architecture that can be configured by programming two of the internal control registers. SPORT2 has three distinct modes of operation: Control Mode, Data Mode and Mixed Control/Data Mode. In Control Mode (CRA:0 = 0), the device's internal configuration can be programmed by writing to the five internal control registers. In this mode, control information can be written to or read from the codec. In Data Mode (CRA:0 = 1), information that is sent to the device is used to update the decoder section (DAC), while the encoder section (ADC) data is read from the device. In this mode, only DAC and ADC data is written to or read from the device. Mixed mode (CRA:0 = 1 and CRA:1 = 1) allows the user to choose whether the information being sent to the device contains either control information or DAC data. This is achieved by using the MSB of the 16-bit frame as a flag bit. Mixed mode reduces the resolution to 15 bits, with the MSB being used to indicate whether the information in the 16-bit frame is control information or DAC/ADC data. The SPORT features a single 16-bit serial register that is used for both input and output data transfers. As the input and output data must share the same register some precautions must be observed. The primary precaution is that no information be written to the SPORT without reference to an output sample event, which is when the serial register will be overwritten with the latest ADC sample word. Once the SPORT starts to output the latest ADC word, it is safe for the DSP to write new control or data words to the codec. In certain configurations, data can be written to the device to coincide with the output sample being shifted out of the serial register--see section on interfacing devices. The serial clock rate (CRB:2-3) defines how many 16-bit words can be written to a device before the next output sample event will happen. The SPORT block diagram, shown in Figure 6, details the six control registers (A-F), external MCLK to internal DMCLK divider, and serial clock divider. The divider rates are controlled by the setting of Control Register B. The AD73411 features a master clock divider that allows users the flexibility of dividing externally available high-frequency DSP or CPU clocks to generate a lower frequency master clock internally in the codec which may be more suitable for either serial transfer or sampling rate requirements. The master clock divider has five divider options (/ 1 default condition, / 2, / 3, / 4, / 5) that are set by loading the master clock divider field in Register B with the appropriate code. Once the internal device master clock (DMCLK) has been set using the master clock divider, the sample rate and serial clock settings are derived from DMCLK. The SPORT can work at four different serial clock (SCLK) rates: chosen from DMCLK, DMCLK/2, DMCLK/4, or DMCLK/8, where DMCLK is the internal or device master clock resulting from the external or pin master clock being divided by the
master clock divider. When working at the lower SCLK rate of DMCLK/8, which is intended for interfacing with slower DSPs, the SPORT will support a maximum of two devices in cascade with the sample rate of DMCLK/256.
SPORT2 Register Maps
There are two register banks for the AD73411: the control register bank and the data register bank. The control register bank consists of six read/write registers, each eight bits wide. Table VII shows the control register map for the AD73411. The first two control registers, CRA and CRB, are reserved for controlling the SPORT. They hold settings for parameters such as bit rate, internal master clock rate, and device count (used when more than one AFE is connected in cascade from a single SPORT). The other three registers; CRC, CRD, and CRE are used to hold control settings for the ADC, DAC, Reference, and Power Control sections of the device. Control registers are written to on the negative edge of SCLK. The data register bank consists of two 16-bit registers that are the DAC and ADC registers.
Master Clock Divider
The AD73411 features a programmable master clock divider that allows the user to reduce an externally available master clock, at pin MCLK, by one of the ratios 1, 2, 3, 4, or 5, to produce an internal master clock signal (DMCLK) that is used to calculate the sampling and serial clock rates. The master clock divider is programmable by setting CRB:4-6. Table III shows the division ratio corresponding to the various bit settings. The default divider ratio is divide-by-one.
Table III. DMCLK (Internal) Rate Divider Settings
MCD2 0 0 0 0 1 1 1 1
MCD1 0 0 1 1 0 0 1 1
MCD0 0 1 0 1 0 1 0 1
DMCLK Rate MCLK MCLK/2 MCLK/3 MCLK/4 MCLK/5 MCLK MCLK MCLK
Serial Clock Rate Divider
The AD73411 features a programmable serial clock divider that allows users to match the serial clock (SCLK) rate of the data to that of the DSP engine or host processor. The maximum SCLK rate available is DMCLK and the other available rates are: DMCLK/2, DMCLK/4, and DMCLK/8. The slowest rate (DMCLK/8) is the default SCLK rate. The serial clock divider is programmable by setting bits CRB:2-3. Table IV shows the serial clock rate corresponding to the various bit settings.
Table IV. SCLK Rate Divider Settings
SCD1 0 0 1 1
SCD0 0 1 0 1
SCLK Rate DMCLK/8 DMCLK/4 DMCLK/2 DMCLK
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MCLK (EXTERNAL) MCLK DIVIDER DMCLK (INTERNAL)
SE RESET SDIFS SDI
SERIAL PORT (SPORT) SERIAL REGISTER
SCLK DIVIDER
SCLK SDOFS SDO
2 8 3 8 8 8 8 8
CONTROL REGISTER A
CONTROL REGISTER B
CONTROL REGISTER C
CONTROL REGISTER D
CONTROL REGISTER E
CONTROL REGISTER F
Figure 6. SPORT Block Diagram
Sample Rate Divider
The AD73411 features a programmable sample rate divider that allows users flexibility in matching the codec's ADC and DAC sample rates to the needs of the DSP software. The maximum sample rate available is DMCLK/256, which offers the lowest conversion group delay, while the other available rates are: DMCLK/512, DMCLK/1024, and DMCLK/2048. The slowest rate (DMCLK/2048) is the default sample rate. The sample rate divider is programmable by setting bits CRB:0-1. Table V shows the sample rate corresponding to the various bit settings.
Table V. Sample Rate Divider Settings
OPERATION Resetting the AFE Section of the AD73411
DIR1 0 0 1 1
DAC Advance Register
DIR0 0 1 0 1
SCLK Rate DMCLK/2048 DMCLK/1024 DMCLK/512 DMCLK/256
The RESET pin resets all the control registers. All registers are reset to zero, indicating that the default SCLK rate (DMCLK/8) and sample rate (DMCLK/2048) are at a minimum to ensure that slow speed DSP engines can communicate effectively. As well as resetting the control registers using the RESET pin, the device can be reset using the RESET bit (CRA:7) in Control Register A. Both hardware and software resets require four DMCLK cycles. On reset, DATA/PGM (CRA:0) is set to 0 (default condition) thus enabling Program Mode. The reset conditions ensure that the device must be programmed to the correct settings after power-up or reset. Following a reset, the SDOFS will be asserted 2048 DMCLK cycles after RESET going high. The data that is output following RESET and during Program Mode is random and contains no valid information until either Data or Mixed Mode is set.
Power Management
The loading of the DAC is internally synchronized with the unloading of the ADC data in each sampling interval. The default DAC load event happens one SCLK cycle before the SDOFS flag is raised by the ADC data being ready. However, this DAC load position can be advanced before this time by modifying the contents of the DAC Advance field in Control Register E (CRE:0-4). The field is five bits wide, allowing 31 increments of weight 1/(DMCLK/8); see Table VI. In certain circumstances this can reduce the group delay when the ADC and DAC are used to process data in series. Note: The DAC advance register should be changed before the DAC section is powered up.
Table VI. DAC Timing Control
The individual functional blocks of the AFE can be enabled separately by programming the power control register CRC. It allows certain sections to be powered down if not required, which adds to the device's flexibility in that the user need not incur the penalty of having to provide power for a certain section if it is not necessary to their design. The power control register provides individual control settings for the major functional blocks and also a global override that allows all sections to be powered up by setting the bit. Using this method the user could, for example, individually enable a certain section, such as the reference (CRC:5), and disable all others. The global power-up (CRC:0) can be used to enable all sections but if power-down is required using the global control, the reference will still be enabled, in this case, because its individual bit is set. Refer to Table XI for details of the settings of CRC.
DA4 0 0 0 -- 1 1
DA3 0 0 0 -- 1 1
DA2 0 0 0 -- 1 1
DA1 0 0 1 -- 1 1
DA0 0 1 0 -- 0 1
Time Advance* 0 ns 488.2 ns 976.5 ns -- 14.64 s 15.13 s
*DMCLK = 16.384 MHz.
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Table VII. Control Register Map
Address (Binary) 000 001 010 011 100 101 110 to 111
Name CRA CRB CRC CRD CRE CRF
Description Control Register A Control Register B Control Register C Control Register D Control Register E Control Register F Reserved
Type R/W R/W R/W R/W R/W R/W
Width 8 8 8 8 8 8
Reset Setting (Hex) 0x00 0x00 0x00 0x00 0x00 0x00
Table VIII. Control Word Description
15 C/D
14 R/W
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Device Address
Register Address
Register Data
Control Bit 15
Frame Control/Data
Description When set high, it signifies a control word in Program or Mixed Program/Data Modes. When set low, it signifies a data word in Mixed Program/Data Mode or an invalid control word in Program Mode. When set low, it tells the device that the data field is to be written to the register selected by the register field setting provided the address field is zero. When set high, it tells the device that the selected register is to be written to the data field in the input serial register and that the new control word is to be output from the device via the serial output. This 3-bit field holds the address information. Only when this field is zero is a device selected. If the address is not zero, it is decremented and the control word is passed out of the device via the serial output. This 3-bit field is used to select one of the five control registers on the AD73411. This 8-bit field holds the data that is to be written to or read from the selected register provided the address field is zero.
Bit 14
Read/Write
Bits 13-11
Device Address
Bits 10-8 Bits 7-0
Register Address Register Data
Table IX. Control Register A Description CONTROL REGISTER A 7 RESET 6 DC2 5 DC1 4 DC0 3 SLB 2 DLB 1 MM 0 DATA/PGM
Bit 0 1 2 3 4 5 6 7
Name DATA/PGM MM DLB SLB DC0 DC1 DC2 RESET
Description Operating Mode (0 = Program; 1 = Data Mode) Mixed Mode (0 = Off; 1 = Enabled) Digital Loop-Back Mode (0 = Off; 1 = Enabled) SPORT Loop-Back Mode (0 = Off; 1 = Enabled) Device Count (Bit 0) Device Count (Bit 1) Device Count (Bit 2) Software Reset (0 = Off; 1 = Initiates Reset)
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Table X. Control Register B Description CONTROL REGISTER B 7 CEE 6 MCD2 5 MCD1 4 MCD0 3 SCD1 2 SCD0 1 DIR1 0 DIR0
Bit 0 1 2 3 4 5 6 7
Name DIR0 DIR1 SCD0 SCD1 MCD0 MCD1 MCD2 CEE
Description Decimation/Interpolation Rate (Bit 0) Decimation/Interpolation Rate (Bit 1) Serial Clock Divider (Bit 0) Serial Clock Divider (Bit 1) Master Clock Divider (Bit 0) Master Clock Divider (Bit 1) Master Clock Divider (Bit 2) Control Echo Enable (0 = Off; 1 = Enabled)
Table XI. Control Register C Description CONTROL REGISTER C 7 RES 6 RU 5 PUREF 4 PUDAC 3 PUADC 2 RES 1 RES 0 PU
Bit 0 1 2 3 4 5 6 7
Name PU Reserved Reserved PUADC PUDAC PUREF RU Reserved
Description Power-Up Device (0 = Power Down; 1 = Power-On) Must Be Programmed to Zero (0) Must Be Programmed to Zero (0) ADC Power (0 = Power Down; 1 = Power On) DAC Power (0 = Power Down; 1 = Power On) REF Power (0 = Power Down; 1 = Power On) REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT) Must Be Programmed to Zero (0)
Table XII. Control Register D Description CONTROL REGISTER D 7 MUTE 6 OGS2 5 OGS1 4 3 2 IGS2 1 IGS1 0 IGS0
OGS0 RMOD
Bit 0 1 2 3 4 5 6 7
Name IGS0 IGS1 IGS2 RMOD OGS0 OGS1 OGS2 MUTE
Description Input Gain Select (Bit 0) Input Gain Select (Bit 1) Input Gain Select (Bit 2) Reset ADC Modulator (0 = Off; 1 = Reset Enabled) Output Gain Select (Bit 0) Output Gain Select (Bit 1) Output Gain Select (Bit 2) Output Mute (0 = Mute Off; 1 = Mute Enabled)
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Table XIII. Control Register E Description CONTROL REGISTER E 7 RES 6 RES 5 IBYP 4 DA4 3 DA3 2 DA2 1 DA1 0 DA0
Bit 0 1 2 3 4 5 6 7
Name DA0 DA1 DA2 DA3 DA4 IBYP Reserved Reserved
Description DAC Advance Setting (Bit 0) DAC Advance Setting (Bit 1) DAC Advance Setting (Bit 2) DAC Advance Setting (Bit 3) DAC Advance Setting (Bit 4) Interpolator Bypass (0 = Bypass Disabled; 1 = Bypass Enabled) Must Be Programmed to Zero (0) Must Be Programmed to Zero (0)
Table XIV. Control Register F Description CONTROL REGISTER F 7 ALB 6 INV 5 SEEN 4 RES 3 RES 2 RES 1 RES 0 RES
Bit 0 1 2 3 4 5 6 7
Name Reserved Reserved Reserved Reserved Reserved SEEN INV ALB
Description Must Be Programmed to Zero (0) Must Be Programmed to Zero (0) Must Be Programmed to Zero (0) Must Be Programmed to Zero (0) Must Be Programmed to Zero (0) Single-Ended Enable (0 = Disabled; 1 = Enabled) Input Invert (0 = Disabled; 1 = Enabled) Analog Loopback of Output to Input (0 = Disabled; 1 = Enabled)
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AFE Operating Modes
Five operating modes are available on the AFE. Two of these-- Digital Loop-Back and Sport Loop-Back--are provided as diagnostic modes with the other three, Program, Data and Mixed Program/Data, being available for general-purpose use. The device configuration--register settings--can be changed only in Program, and Mixed Program/Data Modes. In all modes, transfers of information to or from the device occur in 16-bit packets, therefore the DSP engine's SPORT will be programmed for 16-bit transfers.
Program (Control) Mode
received at the SDIFS pin. When that number equals the device count stored in the device count field of CRA, the device knows that the present data frame being received is its own DAC update data. When the device is in normal Data Mode (i.e., mixed mode disabled), it must receive a hardware reset to reprogram any of the control register settings. In a single codec configuration, each 16-bit data frame sent from the DSP to the device is interpreted as DAC data. The default device count is 1, therefore each input frame sync will cause the 16-bit data frame to be loaded to the DAC register.
Mixed Program/Data Mode
In Program Mode, CRA:0 = 0, the user writes to the control registers to set up the device for desired operation--SPORT operation, cascade length, power management, input/output gain, etc. In this mode, the 16-bit information packet sent to the device by the DSP engine is interpreted as a control word whose format is shown in Table VIII. In this mode, the user must address the device to be programmed using the address field of the control word. This field is read by the device and if it is zero (000 bin), the device recognizes the word as being addressed to it. If the address field is not zero, it is then decremented and the control word is passed out of the device--either to the next device in a cascade or back to the DSP engine. This 3-bit address format allows the user to uniquely address any one of up to eight devices in a cascade; please note that this addressing scheme is valid only in sending control information to the device--a different format is used to send DAC data to the device(s). In a single codec configuration, all control word addresses must be zero, otherwise they will not be recognized; in a multicodec configuration all addresses from zero to N-1 (where N = number of devices in cascade) are valid. Following reset, when the SE pin is enabled, the codec responds by raising the SDOFS pin to indicate that an output sample event has occurred. Control words can be written to the device to coincide with the data being sent out of the SPORT, as shown in Figure 7, or they can lag the output words by a time interval that should not exceed the sample interval. After reset, output frame sync pulses will occur at a slower default sample rate, which is DMCLK/2048, until Control Register B is programmed, after which the SDOFS pulses will occur at a rate set by the DIR0-1 bits of CRB. This is to allow slow controller devices to establish communication with the AFE. During Program Mode, the data output by the device is random and should not be interpreted as ADC data.
Data Mode
This mode allows the user to send control words to the device along with the DAC data. This permits adaptive control of the device whereby control of the input/output gains can be affected by interleaving control words along with the normal flow of DAC data. The standard data frame remains 16 bits, but now the MSB is used as a flag bit to indicate whether the remaining 15 bits of the frame represent DAC data or control information. In the case of DAC data, the 15 bits are loaded with MSB justification and LSB set to 0 to the DAC register. Mixed Mode is enabled by setting the MM bit (CRA:1) to 1 and the DATA/PGM bit (CRA:0) to 1. In the case where control setting changes will be required during normal operation, this mode allows the ability to load both control and data information with the slight inconvenience of formatting the data. Note that the output samples from the ADC will also have the MSB set to zero to indicate it is a data word.
Digital Loop-Back
This mode can be used for diagnostic purposes and allows the user to feed the ADC samples from the ADC register directly to the DAC register. This forms a loop-back of the analog input to the analog output by reconstructing the encoded signal using the decoder channel. The serial interface will continue to work, which allows the user to control gain settings, etc. Only when DLB is enabled with Mixed Mode operation can the user disable the DLB, otherwise the device must be reset.
Sport Loop-Back
This mode allows the user to verify the DSP interfacing and connection by writing words to the SPORT of the device and have them returned back unchanged at the next sample interval. The frame sync and data word that are sent to the device are returned via the output port. Again, SLB mode can only be disabled when used in conjunction with mixed mode, otherwise the device must be reset.
Analog Loop-Back
Once the device has been configured by programming the correct settings to the various control registers, the device may exit Program Mode and enter Data Mode. This is done by programming the DATA/PGM (CRA:0) bit to a 1 and MM (CRA:1) to 0. Once the device is in Data Mode, the 16-bit input data frame is now interpreted as DAC data rather than a control frame. This data is therefore loaded directly to the DAC register. In Data Mode, as the entire input data frame contains DAC data, the device relies on counting the number of input frame syncs
In Analog Loop-Back mode, the differential DAC output is connected, via a loop-back switch, to the ADC input (see Figure 9). This mode allows the ADC channel to check functionality of the DAC channel as the reconstructed output signal can be monitored using the ADC as a sampler. Analog Loop-Back is enabled by setting the ALB bit (CRF:7).
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AD73411
SE
SCLK
SDOFS
SDO
SAMPLE WORD (DEVICE 1)
SAMPLE WORD (DEVICE 1)
SDIFS
SDI
DATA (CONTROL) WORD (DEVICE 1)
DATA (CONTROL) WORD (DEVICE 1)
Figure 7. Interface Signal Timing for Single Device Operation
SE
SCLK
SDOFS(2)
SDO(2)
SAMPLE WORD (DEVICE 2)
SAMPLE WORD (DEVICE 1)
SDOFS(1) SDIFS(2)
SDO(1) SDI(2)
SAMPLE WORD (DEVICE 1)
DATA (CONTROL) WORD (DEVICE 2)
SDIFS(1)
SDI(1)
DATA (CONTROL) WORD (DEVICE 2)
DATA (CONTROL) WORD (DEVICE 1)
Figure 8. Interface Signal Timing for Cascade of Two Devices
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AD73411
ANALOG LOOP-BACK SELECT
TFS SDIFS SDI SCLK
INVERT
SINGLE-ENDED ENABLE
DT
VINP 0/38dB PGA VINN
DSP SECTION
SCLK
AFE SECTION
DR RFS
SDO SDOFS
VREF VOUTP VOUTN REFOUT REFCAP +6/-15dB PGA CONTINUOUS TIME LOW-PASS FILTER
Figure 10. Indirectly Coupled or Nonframe Sync LoopBack Configuration
AD73411
REFERENCE
Cascade Operation
Figure 9. Analog Loop-Back Connectivity
AFE Interfacing
The AFE section SPORT (SPORT2) can be interfaced to either SPORT0 or SPORT1 of the DSP section. Both serial input and output data use an accompanying frame synchronization signal which is active high one clock cycle before the start of the 16-bit word or during the last bit of the previous word if transmission is continuous. The serial clock (SCLK) is an output from the codec and is used to define the serial transfer rate to the DSP's Tx and Rx ports. Two primary configurations can be used: the first is shown in Figure 10 where the DSP's Tx data, Tx Frame Sync, Rx data and Rx Frame Sync are connected to the codec's SDI, SDIFS, SDO and SDOFS respectively. This configuration, referred to as indirectly coupled or nonframe sync loop-back, has the effect of decoupling the transmission of input data from the receipt of output data. The delay between receipt of codec output data and transmission of input data for the codec is determined by the DSP's software latency. When programming the DSP serial port for this configuration, it is necessary to set the Rx Frame Sync as an input and the Tx Frame Sync as an output generated by the DSP. This configuration is most useful when operating in mixed mode, as the DSP has the ability to decide how many words (either DAC or control) can be sent to the codecs. This means that full control can be implemented over the device configuration as well as updating the DAC in a given sample interval. The second configuration (shown in Figure 11) has the DSP's Tx data and Rx data connected to the codec's SDI and SDO, respectively while the DSP's Tx and Rx frame syncs are connected to the codec's SDIFS and SDOFS. In this configuration, referred to as directly coupled or frame sync loop-back, the frame sync signals are connected together and the input data to the codec is forced to be synchronous with the output data from the codec. The DSP must be programmed so that both the Tx Frame Sync and Rx Frame Sync are inputs as the codec SDOFS will be input to both. This configuration guarantees that input and output events occur simultaneously and is the simplest configuration for operation in normal Data Mode. Note that when programming the DSP in this configuration it is advisable to preload the Tx register with the first control word to be sent before the codec is taken out of reset. This ensures that this word will be transmitted to coincide with the first output word from the device(s).
The AD73411 has been designed to support up to eight codecs in a cascade connected to a single serial port. The SPORT interface protocol has been designed so that device addressing is built into the packet of information sent to the device. This allows the cascade to be formed with no extra hardware overhead for control signals or addressing. A cascade can be formed in either of the two modes previously discussed. There may be some restrictions in cascade operation due to the number of devices configured in the cascade and the serial clock rate chosen. Table XV details the requirements for SCLK rate for cascade lengths from 1 to 8 devices. This assumes a directly coupled frame sync arrangement as shown in Figure 11.
Table XV. Cascade Options
SCLK DMCLK DMCLK/2 DMCLK/4 DMCLK/8
1
Number of Devices in Cascade 2 3 4 5 6 7
TFS DT SCLK DR RFS
8 X X
X
X
SDIFS SDI
X X
X X
X X
DSP SECTION
SCLK
AFE SECTION
SDO SDOFS
Figure 11. Directly Coupled or Frame Sync LoopBack Configuration
When using the indirectly coupled frame sync configuration in cascaded operation it is necessary to be aware of the restrictions in sending data to all devices in the cascade. Effectively, the time allowed is given by the sampling interval (256/DMCLK) which is 15.625 s for a sample rate of 64 kHz. In this interval, the DSP must transfer N x 16 bits of information where N is the number of devices in the cascade. Each bit will take 1/SCLK and, allowing for any latency between the receipt of the Rx interrupt and the transmission of the Tx data, the relationship for successful operation is given by: 256/DMCLK > ((N x 16/SCLK) + TINTERRUPT LATENCY) The interrupt latency will include the time between the ADC sampling event and the Rx interrupt being generated in the DSP--this should be 16 SCLK cycles.
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In Cascade Mode, each device must know the number of devices in the cascade because the Data and Mixed modes use a method of counting input frame sync pulses to decide when they should update the DAC register from the serial input register. Control Register A contains a 3-bit field (DC0-2) that is programmed by the DSP during the programming phase. The default condition is that the field contains 000b, which is equivalent to a single device in cascade (see Table XVI). For cascade operation, however this field must contain a binary value that is one less than the number of devices in the cascade.
Table XVI. Device Count Settings
accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. The shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the AD73411 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Efficient data transfer is achieved with the use of five internal buses: * * * * * Program Memory Address (PMA) Bus Program Memory Data (PMD) Bus Data Memory Address (DMA) Bus Data Memory Data (DMD) Bus Result (R) Bus
DC2 0 0 0 0 1 1 1 1
DC1 0 0 1 1 0 0 1 1
DC0 0 1 0 1 0 1 0 1
Cascade Length 1 2 3 4 5 6 7 8
FUNCTIONAL DESCRIPTION--DSP
The AD73411 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The AD73411 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.
POWER-DOWN CONTROL DATA ADDRESS GENERATORS DAG 1 DAG 2 MEMORY 16K PM 16K DM
(OPTIONAL (OPTIONAL 8K) 8K)
FULL MEMORY MODE PROGRAMMABLE I/O AND FLAGS EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER OR EXTERNAL DATA BUS TIMER INTERNAL DMA PORT HOST MODE
PROGRAM SEQUENCER
PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS
The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting the AD73411 to fetch two operands in a single cycle, one from program memory and one from data memory. The AD73411 can fetch an operand from program memory and the next instruction in the same cycle. In lieu of the address and data bus for external memory connection, the AD73411 may be configured for 16-bit Internal DMA port (IDMA port) connection to external systems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSPs on-chip program and data RAM. An interface to low-cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the AD73411 to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. -21-
PROGRAM MEMORY DATA DATA MEMORY DATA
ARITHMETIC UNITS ALU MAC SHIFTER ADSP-2100 BASE ARCHITECTURE
SERIAL PORTS SPORT 0 SPORT 1
REF
SERIAL PORT SPORT 2
ADC1
DAC1
ANALOG FRONT END SECTION
Figure 12. Functional Block Diagram
Figure 12 is an overall block diagram of the AD73411. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of
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AD73411
The AD73411 can respond to eleven interrupts. There can be up to six external interrupts (one edge-sensitive, two levelsensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. The AD73411 provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs and three flags are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD).
Serial Ports DSP SECTION PIN DESCRIPTIONS
The AD73411 is available in a 119-ball PBGA package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt, and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics. See Pin Function Descriptions section.
Memory Interface Pins
The AD73411 processor can be used in one of two modes, Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running. See Full Memory Mode Pins and Host Mode Pins charts for descriptions.
Full Memory Mode Pins (Mode C = 0)
Pin Name(s) A13:0 D23:0
# of Pins 14 24
Input/ Output Function O I/O Address Output Pins for Program, Data, Byte, and I/O Spaces Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory addresses)
The DSP section incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Following is a brief list of the capabilities of the SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User's Manual, Third Edition. * SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section. * SPORTs can use an external serial clock or generate their own serial clock internally. * SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings. * SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and -law companding according to CCITT recommendation G.711. * SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. * SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. * SPORT0 has a multichannel interface to selectively receive and transmit a 24- or 32-word, time-division multiplexed, serial bitstream. * SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration.
Host Mode Pins (Mode C = 1)
Pin Name(s) IAD15:0 A0 D23:8 IWR IRD IAL IS IACK
# of Pins 16 1 16 1 1 1 1 1
Input/ Output Function I/O O I/O I I I I O IDMA Port Address/Data Bus Address Pin for External I/O, Program, Data, or Byte Access Data I/O Pins for Program, Data Byte and I/O Spaces IDMA Write Enable IDMA Read Enable IDMA Address Latch Pin IDMA Select IDMA Port Acknowledge
NOTE In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.
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Terminating Unused Pin
The following chart shows the recommendations for terminating unused pins.
Pin Terminations
Pin Name XTAL CLKOUT A13:1 or IAD12:0 A0 D23:8 D7 or IWR D6 or IRD D5 or IAL D4 or IS D3 or IACK D2:0 or IAD15:13 PMS DMS BMS IOMS CMS RD WR BR BG BGH IRQ2/PF7 I/O 3-State (Z) I O O (Z) I/O (Z) O (Z) I/O (Z) I/O (Z) I I/O (Z) I I/O (Z) I I/O (Z) I I/O (Z) I/O (Z) I/O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) I O (Z) O I/O (Z) Reset State I O Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z I Hi-Z I Hi-Z I Hi-Z I Hi-Z Hi-Z Hi-Z O O O O O O O I O O I Hi-Z* Caused By Unused Configuration Float Float Float Float Float Float Float High (Inactive) Float High (Inactive) Float Low (Inactive) Float High (Inactive) Float Float Float Float Float Float Float Float Float Float Float High (Inactive) Float Float Input = High (Inactive) or Program as Output, Set to 1, Let Float Input = High (Inactive) or Program as Output, Set to 1, Let Float Input = High (Inactive) or Program as Output, Set to 1, Let Float Input = High (Inactive) or Program as Output, Set to 1, Let Float Input = High or Low, Output = Float High or Low High or Low High or Low Float Input = High or Low, Output = Float High or Low High or Low High or Low Float
BR, EBR IS BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR IS BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR EE
NOTES *Hi-Z = High Impedance. 1. If the CLKOUT pin is not used, turn it OFF. 2. If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1, and let them float. 3. All bidirectional pins have three-stated outputs. When the pins is configured as an output, the output is Hi-Z (high impedance) when inactive. 4. CLKIN, RESET, and PF3:0 are not included in the table because these pins must be used.
Interrupts
The interrupt controller allows the processor to respond to the eleven possible interrupts and RESET with minimum overhead. The AD73411 provides four dedicated external interrupt input pins, IRQ2, IRQL0, IRQL1, and IRQE. In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN, and FLAG_OUT, for a total of six external interrupts. The AD73411 also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software, and the powerdown control circuit. The interrupt levels are internally prioritized and individually maskable (except power-down and reset). The IRQ2, IRQ0, and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are levelsensitive and IRQE is edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table XVII.
Table XVII. Interrupt Priority and Interrupt Vector Addresses
Source of Interrupt RESET (or Power-Up with PUCR = 1) Power-Down (Nonmaskable) IRQ2 IRQL1 IRQL0 SPORT0 Transmit SPORT0 Receive IRQE BDMA Interrupt SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Timer
Interrupt Vector Address (Hex) 0000 (Highest Priority) 002C 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 (Lowest Priority)
IRQL1/PF6 I/O (Z) IRQL0/PF5 I/O (Z) IRQE/PF4
I
I
I/O (Z)
I
SCLK0 RFS0 DR0 TFS0 DT0 SCLK1 RFS1/IRQ0 DR1/FI TFS1/IRQ1 DT1/FO EE EBR EBG ERESET EMS EINT ECLK ELIN ELOUT
I/O I/O I I/O O I/O I/O I I/O O I I O I O I I I O
I I I O O I I I O O I I O I O I I I O
Interrupt routines can either be nested, with higher priority interrupts taking precedence, or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. The AD73411 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers. The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1, and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge-sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level-sensitive interrupts. The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks -23-
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are twelve levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global enable or disable servicing of the interrupts (including power-down), regardless of the state of IMASK. Disabling the interrupts does not affect serial port autobuffering or DMA. ENA INTS; DIS INTS; When the processor is reset, interrupt servicing is enabled.
LOW-POWER OPERATION
clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is IDLE (n); where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor's other internal clock signals, such as SCLK, CLKOUT, and Timer Clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. When the IDLE (n) instruction is used, it effectively slows down the processor's internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the AD73411 will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor's reduced internal clock rate. Under these conditions, interrupts must not be generated at a rate faster than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles).
SYSTEM INTERFACE
The AD73411 has three low-power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are: * Power-Down * Idle * Slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation.
Power-Down
The AD73411 processor has a low-power feature that lets the processor enter a very low-power dormant state through hardware or software control. Here is a brief list of power-down features. Refer to the ADSP-2100 Family User's Manual, Third Edition, "System Interface" chapter, for detailed information about the power-down feature. * Quick recovery from power-down. The processor begins executing instructions in as few as 400 CLKIN cycles. * Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during power-down without affecting the 400 CLKIN cycle recovery. * Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits 4096 CLKIN cycles for the crystal oscillator to start and stabilize), and letting the oscillator run to allow 400 CLKIN cycle startup. * Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit. Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The power-down interrupt also can be used as a nonmaskable, edge-sensitive interrupt. * Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. * The RESET pin also can be used to terminate power-down. * Power-down acknowledge pin indicates when the processor has entered power-down.
Idle
Figure 13 shows a typical basic system configuration with the AD73411, two serial devices, a byte-wide EPROM, and optional external program and data overlay memories (mode selectable). Programmable wait state generation allows the processor to connect easily to slow peripheral devices. The AD73411 also provides four external interrupts and two serial ports or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to a single address bit (A0). Additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals.
Clock Signals
The AD73411 can be clocked by either a crystal or a TTLcompatible clock signal. The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency during normal operation. The only exception is while the processor is in the power-down state. For detailed information on this power-down feature, refer to Chapter 9, ADSP-2100 Family User's Manual, Third Edition. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor's CLKIN input. When an external clock is used, the XTAL input must be left unconnected. The AD73411 uses an input clock with a frequency equal to half the instruction rate; a 26.00 MHz input clock yields a 19 ns processor cycle (which is equivalent to 52 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled.
When the AD73411 is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle Mode IDMA, BDMA, and Autobuffer Cycle steals still occur.
Slow Idle
The IDLE instruction on the AD73411 slows the processor's internal clock signal, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal -24- REV. 0
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FULL MEMORY MODE
AD73411
1/2x CLOCK OR CRYSTAL CLKIN XTAL FL0-2 PF3 IRQ2/PF7 IRQE/PF4 IRQL0/PF5 IRQL1/PF6 MODE C/PF2 MODE B/PF1 MODE A/PF0 AFE* SECTION OR SERIAL DEVICE SPORT1 SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI SPORT0 SCLK0 RFS0 TFS0 DT0 DR0 ADDR13-0
14
A13-0 D23-16 A0-A21 BYTE MEMORY DATA CS A10-0 ADDR D23-8 I/O SPACE (PERIPHERALS) DATA 2048 LOCATIONS CS
A clock output (CLKOUT) signal is generated by the processor at the processor's cycle rate. This can be enabled and disabled by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.
Reset
24 DATA23-0 BMS WR RD IOMS
D15-8
A13-0 D23-0 PMS DMS CMS BR BG BGH PWD PWDACK ADDR OVERLAY MEMORY DATA TWO 8K PM SEGMENTS TWO 8K DM SEGMENTS
The RESET signal initiates a master reset of the DSP section of the AD73411. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, tRSP. The RESET input contains some hysteresis; however, if an RC circuit is used to generate the RESET signal, an external Schmitt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. Once boot loading completes, the first instruction is fetched from on-chip program memory location 0x0000.
MODES OF OPERATION
AFE* SECTION OR SERIAL DEVICE
HOST MEMORY MODE
AD73411
1/2x CLOCK OR CRYSTAL CLKIN XTAL FL0-2 PF3 IRQ2/PF7 IRQE/PF4 IRQL0/PF5 IRQL1/PF6 MODE C/PF2 MODE B/PF1 MODE A/PF0 AFE* SECTION OR SERIAL DEVICE A0 DATA23-8 BMS
1 16
WR RD
SPORT1 IOMS SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 PMS DT1 OR FO DMS DR1 OR FI CMS SPORT0 SCLK0 RFS0 TFS0 DT0 DR0 BR BG BGH PWD PWDACK
Table XVII summarizes the AD73411 memory modes.
Setting Memory Mode
AFE* SECTION OR SERIAL DEVICE
Memory Mode selection for the AD73411 is made during chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP's PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive. Passive Configuration involves the use a pull-up or pull-down resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a weak pull-up or pull-down, on the order of 100 k, can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor's output driver. For minimum power consumption during power-down, reconfigure PF2 to be an input, as the pull-up or pull-down will hold the pin in a known state and will not switch. Active Configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver's output enable should be connected to the DSP's RESET signal such that it only drives the PF2 pin when RESET is active (low). When RESET is deasserted, the driver should three-state, thus allowing full use of the PF2 pin as either an input or output. To minimize power consumption during power-down, configure the programmable flag as an output when connected to a three-stated buffer. This ensures that the pin will be held at a constant level and not oscillate should the three-state driver's level hover around the logic switching point. -25-
SYSTEM INTERFACE OR CONTROLLER 16
IDMA PORT IRD/D6 IWR/D7 IS/D4 IAL/D5 IACK/D3 IAD15-0
*AFE SECTION CAN BE CONNECTED TO EITHER SPORT0 OR SPORT1
Figure 13. Basic System Configuration
CLKIN
XTAL
CLKOUT
DSP
Figure 14. External Crystal Connections
Because the AD73411 includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 14. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. REV. 0
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Table XVIII. Modes of Operations1
MODE C2 0
MODE B3 0
MODE A4 0
Booting Method BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Full Memory Mode.5 No automatic boot operations occur. Program execution starts at external memory location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does not automatically use or wait for these operations. BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode.6 IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode.5
0
1
0
1
0
0
1
0
1
NOTES 1 All mode pins are recognized while RESET is active (low). 2 When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled. 3 When Mode B = 0, Autobooting enabled. When Mode B = 1, no Autobooting. 4 When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled. 5 Considered as standard operating settings. Using these configurations allows for easier design and better memory management. 6 Requires additional hardware.
MEMORY ARCHITECTURE
PM (MODE B = 0) ALWAYS ACCESSIBLE AT ADDRESS 0x0000 - 0x1FFF ACCESSIBLE WHEN PMOVLAY = 0 0x2000- 0x3FFF 0x2000- 0x3FFF2 0x2000- 0x3FFF2
PM (MODE B = 1)1 RESERVED INTERNAL MEMORY ACCESSIBLE WHEN PMOVLAY = 0 ACCESSIBLE WHEN PMOVLAY = 0 EXTERNAL MEMORY SET TO 0
2SEE TABLE XIX FOR PMOVLAY
The AD73411 provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to the following figures and tables for PM and DM memory allocations in the AD73411.
PROGRAM MEMORY
INTERNAL MEMORY
0x2000- 0x3FFF 0x0000- 0x1FFF2
Program Memory (Full Memory Mode) is a 24-bit-wide space for storing both instruction op codes and data. The AD73411-80 has 16K words of Program Memory RAM on chip (the AD73411-40 has 8K words of Program Memory RAM on chip), and the capability of accessing up to two 8K external memory overlay spaces using the external data bus. Program Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). External program execution is not available in host mode due to a restricted data bus that is only 16 bits wide.
Table XIX. PMOVLAY Bits
ACCESSIBLE WHEN PMOVLAY = 1 EXTERNAL ACCESSIBLE MEMORY WHEN PMOVLAY = 2
RESERVED
1WHEN MODE B = 1, PMOVLAY MUST BE
BITS
PROGRAM MEMORY MODE B = 0 ADDRESS 0x3FFF 8K INTERNAL PMOVLAY = 0 OR 8K EXTERNAL PMOVLAY = 1 OR 2 0x2000 0x1FFF 8K INTERNAL 0x0000
PROGRAM MEMORY MODE B = 1 ADDRESS 0x3FFF 8K INTERNAL PMOVLAY = 0 0x2000 0x1FFF 8K EXTERNAL 0x0000
PMOVLAY 0 1
Memory Internal External Overlay 1 External Overlay 2
A13
A12:0
2
Not Applicable Not Applicable 0 13 LSBs of Address Between 0x2000 and 0x3FFF 1 13 LSBs of Address Between 0x2000 and 0x3FFF
Figure 15. Program Memory Map
DATA MEMORY
Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The AD73411-80 has 16K words on Data Memory RAM on-chip (the AD73411-40 has 8K words on Data Memory RAM on-chip), consisting of 16,352 user-accessible locations in the case of the AD73411-80 (8,160 user-accessible locations in the case of the AD73411-40) and 32 memorymapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register.
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REV. 0
AD73411
DATA MEMORY DATA MEMORY
ALWAYS ACCESSIBLE AT ADDRESS 0x2000 - 0x3FFF
32 MEMORY MAPPED REGISTERS
0x0000- 0x1FFF
ADDRESS 0x3FFF
INTERNAL MEMORY ACCESSIBLE WHEN DMOVLAY = 0
INTERNAL 8160 WORDS
0x3FE0 0x3FDF 0x2000 0x1FFF
The CMS pin functions like the other memory select signals, with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits default to 1 at reset, except the BMS bit.
Boot Memory Select (BMS) Disable
0x0000- 0x1FFF 0x0000- 0x1FFF
ACCESSIBLE WHEN DMOVLAY = 1 EXTERNAL MEMORY ACCESSIBLE WHEN DMOVLAY = 2
8K INTERNAL DMOVLAY = 0 OR EXTERNAL 8K DMOVLAY = 1, 2
0x0000
Figure 16. Data Memory Map
Data Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). The DMOVLAY bits are defined in Table XX.
Table XX. DMOVLAY Bits
The AD73411 also lets you boot the processor from one external memory space while using a different external memory space for BDMA transfers during normal operation. You can use the CMS to select the first external memory space for BDMA transfers and BMS to select the second external memory space for booting. The BMS signal can be disabled by setting Bit 3 of the System Control Register to 1. The System Control Register is illustrated in Figure 17.
SYSTEM CONTROL REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 1 0 0 0 0 0 0 0 2 1 1 1 0 1 DM (0x3FFF) PWAIT PROGRAM MEMORY WAIT STATES BMS ENABLE 0 = ENABLED 1 = DISABLED
DMOVLAY 0 1
Memory
A13
A12:0
2
Internal Not Applicable Not Applicable External 0 13 LSBs of Address Overlay 1 Between 0x2000 and 0x3FFF External 1 13 LSBs of Address Overlay 2 Between 0x2000 and 0x3FFF
SPORT0 ENABLE 1 = ENABLED 0 = DISABLED SPORT1 ENABLE 1 = ENABLED 0 = DISABLED SPORT1 CONFIGURE 1 = SERIAL PORT 0 = FI, FO, IRQ0, IRQ1, SCLK
Figure 17. System Control Register
Byte Memory
I/O Space (Full Memory Mode)
The AD73411 supports an additional external memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit-wide data. The lower 11-bits of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100 Family Instruction Set to read from and write to I/O memory space. The I/O space also has four dedicated 3-bit wait state registers, IOWAIT03, that specify up to seven wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table XXI.
Table XXI. Wait States
The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The BDMA Control Register is shown in Figure 18. The byte memory space consists of 256 pages, each of which is 16K x 8. The byte memory space on the AD73411 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg x 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register.
Byte Memory DMA (BDMA, Full Memory Mode)
Address Range Wait State Register 0x000-0x1FF 0x200-0x3FF 0x400-0x5FF 0x600-0x7FF IOWAIT0 IOWAIT1 IOWAIT2 IOWAIT3
The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally, and steals only one DSP cycle per 8-, 16-, or 24-bit word transferred.
15 14 13 12 11 10 0 0 0 0 0 0 BDMA CONTROL 98765 0 0 0 0 0 4 0 3 1 2 0 1 0 0 0 DM (0x3FE3)
Composite Memory Select (CMS)
The AD73411 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality. Each bit in the CMSSEL register, when set, causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory; use either DMS or PMS as the additional address bit. REV. 0
BMPAGE
BTYPE BDIR 0 = LOAD FROM BM 1 = STORE TO BM BCR 0 = RUN DURING BDMA 1 = HALT DURING BDMA
Figure 18. BDMA Control Register
The BDMA circuit supports four different data formats that are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table XXII shows the data formats supported by the BDMA circuit. -27-
AD73411
Table XXII. Data Formats
BTYPE 00 01 10 11
Internal Memory Space Program Memory Data Memory Data Memory Data Memory
4. Host uses IS and IRD (or IWR) to read (or write) DSP internal memory (PM or DM). Alignment Full Word Full Word MSBs LSBs 5. Host checks IACK line to see if the DSP has completed the previous IDMA operation. 6. Host ends IDMA transfer. The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written to while the AD73411 is operating at full speed. The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location; the destination type specifies whether it is a DM or PM access. The falling edge of the address latch signal latches this value into the IDMAA register. Once the address is stored, data can either be read from or written to the AD73411's on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the AD73411 that a particular transaction is required. In either case, there is a one-processor-cycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automatically incremented and another access can occur. Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the AD73411 to write the address onto the IAD0-14 bus into the IDMA Control Register. The IDMAA register, shown below, is memory mapped at address DM (0x3FE0). Note that the latched address (IDMAA) cannot be read back by the host. See Figure 19 for more information on IDMA and DMA memory maps.
IDMA CONTROL (U = UNDEFINED AT RESET) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 U U U U U U U U U U U U U
Word Size 24 16 8 8
Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations. The source or destination of a BDMA transfer will always be on-chip program or data memory. When the BWCOUNT register is written with a nonzero value, the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether or not the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor and start execution at address 0 when the BDMA accesses have completed. The BDMA overlay bits specify the OVLAY memory blocks to be accessed for internal memory.
Internal Memory DMA Port (IDMA Port; Host Memory Mode)
1 U
0 U DM(0x3FE0)
The IDMA Port provides an efficient means of communication between a host system and the AD73411. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot be used, however, to write to the DSP's memorymapped control registers. A typical IDMA transfer process is described as follows: 1. Host starts IDMA transfer. 2. Host checks IACK control line to see if the DSP is busy. 3. Host uses IS and IAL control lines to latch the DMA starting address (IDMAA) into the DSP's IDMA control registers. IAD[15] must be set = 0.
IDMAA ADDRESS IDMAD DESTINATION MEMORY TYPE: 0 = PM 1 = DM
Figure 19. IDMA Control/OVLAY Registers
Bootstrap Loading (Booting)
The AD73411 has two mechanisms to allow automatic loading of the internal program memory after reset. The method for booting after reset is controlled by the Mode A, B and C configuration bits. When the mode pins specify BDMA booting, the AD73411 initiates a BDMA boot sequence when reset is released.
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REV. 0
AD73411
When BDMA booting is specified, the BDMA interface is set up during reset to the following defaults: the BDIR, BMPAGE, BIAD and BEAD registers are set to 0, the BTYPE register is set to 0 to specify program memory 24-bit words, and the BWCOUNT register is set to 32. This causes 32 words of onchip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0. The ADSP-2100 Family Development Software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory-space-compatible boot code. The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the AD73411. A0 is the only memory address bit provided by the processor.
IDMA Port Booting Flag I/O Pins
The AD73411 has eight general-purpose programmable input/ output flag pins. They are controlled by two memory-mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the AD73411's clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. In addition to the programmable flags, the AD73411 has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1, and FL2. FL0-FL2 are dedicated output flags; FLAG_IN and FLAG_OUT are available as an alternate configuration of SPORT1. Note: Pins PF0, PF1, PF2, and PF3 are also used for device configuration during reset.
INSTRUCTION SET DESCRIPTION
The AD73411 can also boot programs through its Internal DMA port. If Mode C = 1, Mode B = 0 and Mode A = 1, the AD73411 boots from the IDMA port. IDMA feature can load as much onchip memory as desired. Program execution is held off until on-chip program memory location 0 is written to.
Bus Request and Bus Grant (Full Memory Mode)
The AD73411 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor's unique architecture, offers the following benefits: * The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation. * Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. * The syntax is a superset ADSP-2100 Family assembly language and is completely source-and object-code-compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the AD73411's interrupt vector and reset vector map. * Sixteen condition codes are available. For conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. * Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE (R)-COMPATIBLE SYSTEM
The AD73411 can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the AD73411 is not performing an external memory access, it responds to the active BR input in the following processor cycle by: * Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers * Asserting the bus grant (BG) signal * Halting program execution If Go Mode is enabled, the AD73411 will not halt program execution until it encounters an instruction that requires an external memory access. If the AD73411 is performing an external memory access when the external device asserts the BR signal, it will not three-state the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, reenables the output drivers and continues program execution from the point at which it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the AD73411 is ready to execute an instruction, but is stopped because the external bus is already granted to another device. The other device can release the bus by deasserting bus request. Once the bus is released, the AD73411 deasserts BG and BGH and executes the external memory access.
EZ-ICE(R) registered trademark of Analog Devices. EZ-ToolsTM registered trademark of Analog Devices.
The AD73411 has on-chip emulation support and an ICE-Port, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE's in-circuit probe, a 14-pin plug. See the ADSP-2100 Family EZ-ToolsTM data sheet for complete information on ICE products. Issuing the chip reset command during emulation causes the DSP to perform a full chip reset, including a reset of its memory mode. Therefore, it is vital that the mode pins are set correctly prior to issuing a chip reset command from the emulator user interface. If you are using a passive method of maintaining mode information (as discussed in Setting Memory Modes), it does not matter that the mode information is latched by an emulator reset. However, if using the RESET pin as a method
REV. 0
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AD73411
of setting the value of the mode pins, the effects of an emulator reset must be taken into consideration. One method of ensuring that the values located on the mode pins are those desired, is to construct a circuit like the one shown in Figure 20. This circuit forces the value located on the Mode A pin to logic high; regardless if it is latched via the RESET or ERESET pin.
ERESET RESET
ing should be 0.1 x 0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-ICE probe plug. Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec.
1 GND 3
EBG
2 4
BG BR
5
EBR
6
EINT
AD73411
1k MODE A/PFO
7 KEY (NO PIN) 9
ELOUT
8
ELIN
PROGRAMMABLE I/O
10
ECLK
Figure 20. Mode A Pin/EZ-ICE Circuit
11
EE
12 14
The ICE-Port interface consists of the following AD73411 pins: EBR EMS ELIN EBG EINT ELOUT ERESET ECLK EE
EMS ERESET
RESET
13
TOP VIEW
These AD73411 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pulldown resistors. The traces for these signals between the AD73411 and the connector must be kept as short as possible, no longer than three inches. The following pins are also used by the EZ-ICE: BR RESET BG GND
Figure 21. Target Board Connector for EZ-ICE
Target Memory Interface
For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed below.
PM, DM, BM, IOM and CM
The EZ-ICE uses the EE (emulator enable) signal to take control of the AD73411 in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. The EZ-ICE connects to your target system via a ribbon cable and a 14-pin female plug. The ribbon cable is 10 inches in length with one end fixed to the EZ-ICE. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM) and Composite Memory (CM) external interfaces to comply with worst-case device timing requirements and switching characteristics as specified in the DSP's data sheet. The performance of the EZ-ICE may approach published worst case specification for some memory access timing requirements and switching characteristics. Note: If your target does not meet the worst-case chip specification for memory access parameters, you may not be able to emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may have trouble manufacturing your system as DSP components statistically vary in switching characteristic and timing requirements within published limits. Restriction: All memory strobe signals on the AD73411 (RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your target system must have 10 k pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed at your option when the EZ-ICE is not being used.
The EZ-ICE connector (a standard pin strip header) is shown in Figure 21. You must add this connector to your target board design if you intend to use the EZ-ICE. Be sure to allow enough room in your system to fit the EZ-ICE probe onto the 14-pin connector. The 14-pin, 2-row pin strip header is keyed at the Pin 7 location--you must remove Pin 7 from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spac-
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AD73411
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some system signals changes. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board: * EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the RESET signal. * EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the BR signal. * EZ-ICE emulation ignores RESET and BR when singlestepping. * EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted). * EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the DSP's external memory bus only if bus grant (BG) is asserted by the EZ-ICE board's DSP.
ANALOG FRONT END (AFE) INTERFACING
of the SE and ARESET signals is synchronized at each device in the cascade. A simple D-type flip-flop is sufficient to sync each signal to the master clock AMCLK, as in Figure 23.
DSP CONTROL TO SE AMCLK DSP CONTROL TO ARESET AMCLK D 1/2 74HC74 CLK ARESET SIGNAL SYNCHRONIZED TO AMCLK Q SE SIGNAL SYNCHRONIZED TO AMCLK
D 1/2 74HC74 CLK
Q
Figure 23. SE and ARESET Sync Circuit for Cascaded Operation
The AFE section of the AD73411 features a voiceband input/ output channel, each with 16-bit linear resolution. Connectivity to the AFE section from the DSP is uncommitted, thus allowing the user the flexibility of connecting in the mode or configuration of their choice. This section will detail several configurations-- with no extra AFE channels configured and with two extra AFE channels configured (using an external AD73322 dual AFE).
DSP SPORT to AFE Interfacing
Connection of a cascade of devices to a DSP, as shown in Figure 24, is no more complicated than connecting a single device. Instead of connecting the SDO and SDOFS to the DSP's Rx port, these are now daisy-chained to the SDI and SDIFS of the next device in the cascade. The SDO and SDOFS of the final device in the cascade are connected to the DSP section's Rx port to complete the cascade. SE and ARESET on all devices are fed from the signals that were synchronized with the AMCLK using the circuit as described above. The SCLK from only one device need be connected to the DSP section's SCLK input(s) as all devices will be running at the same SCLK frequency and phase.
AD73411
AMCLK
The SCLK, SDO, SDOFS, SDI and SDIFS pins of SPORT2 must be connected to the Serial Clock, Receive Data, Receive Data Frame Sync, Transmit Data, and Transmit Data Frame Sync pins respectively of either SPORT0 or SPORT1. The SE pin may be controlled from a parallel output pin or flag pin such as FL0-2 or, where SPORT2 power-down is not required, it can be permanently strapped high using a suitable pull-up resistor. The ARESET pin may be connected to the system hardware reset structure or it may also be controlled using a dedicated control line. In the event of tying it to the global system reset, it is advisable to operate the device in mixed mode, which allows a software reset, otherwise there is no convenient way of resetting the AFE section.
TFS DT SCLK SDIFS SDI SCLK SDO SDOFS ARESET SE
TFS DT
SDIFS SDI SCLK SDO SDOFS DEVICE 1
DSP SECTION
SCLK DR RFS
AFE SECTION
SE ARESET
FL0
FL1
SDIFS SDI
D1 D2 74HC74
Q1 Q2
SCLK SDO SDOFS
ADDITIONAL AD73322 CODEC
DEVICE 2
AMCLK SE ARESET
Figure 24. Connection of an AD73322 Cascaded to AD73411
AFE SECTION
DSP SECTION
DR RFS FL0 FL1
Interfacing to the AFE's Analog Inputs and Outputs
The AFE section of the AD73411 offers a flexible interface for microphone pickups, line level signals, or PSTN line interfaces. This section will detail some of the configurations that can be used with the input and output sections. The AD73411 features both differential inputs and outputs to provide optimal performance and avoid common-mode noise. It is also possible to interface either inputs or outputs in single-ended mode. This section details the choice of input and output configurations and also gives some tips toward successful configuration of the analog interface sections.
Figure 22. AD73411 AFE to DSP Connection
Cascade Operation
Where it is required to configure extra analog I/O channels to the existing two channels on the AD73411, it is possible to cascade up to seven more channels (using single channel AD73311 or dual channel AD73322 AFEs) by using the scheme described in Figure 24. It is necessary, however, to ensure that the timing
REV. 0
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AD73411
ANTIALIAS FILTER
VINP
VINP 0/38dB PGA
VINN
100 0.047 F 0.047 F 100
VINN
0/38dB PGA
VREF
VREF
VOUTP VOUTN
VOUTP VOUTN
+6/-15dB PGA
CONTINUOUS TIME LOW-PASS FILTER
+6/-15dB PGA
CONTINUOUS TIME LOW-PASS FILTER
OPTIONAL BUFFER
REFOUT REFERENCE REFCAP
AD73411
REFOUT REFCAP
REFERENCE
AD73411
0.1 F
0.1 F
Figure 26. Analog Input (DC-Coupled) Using External Amplifiers
Figure 25. Analog Input (DC-Coupled)
Analog Inputs
The analog input (encoder) section of the AD73411 can be interfaced to external circuitry in either ac-coupled or dc-coupled modes. It is also possible to drive the ADC in either differential or single-ended modes. If the single-ended mode is chosen it is possible, using software control, to multiplex between two singleended inputs connected to the positive and negative input pins. The primary concerns in interfacing to the ADC are to provide adequate antialias filtering and to ensure that the signal source will drive the switched-capacitor input of the ADC correctly. The sigma-delta design of the ADC and its oversampling characteristics simplify the antialias requirements, but it must be remembered that the single-pole RC filter is primarily intended to eliminate aliasing of frequencies above the Nyquist frequency of the sigma-delta modulator's sampling rate (typically 2.048 MHz). It may still require a more specific digital filter implementation in the DSP to provide the final signal frequency response characteristics. It is recommended that for optimum performance the capacitors used for the antialiasing filter be of high quality dielectric (NPO). The second issue mentioned above is interfacing the signal source to the ADC's switched capacitor input load. The SC input presents a complex dynamic load to a signal source, therefore, it is important to understand that the slew rate characteristic is an important consideration when choosing external buffers for use with the AD73411. The AD73411's on-chip 38 dB preamplifier can be enabled when there is not enough gain in the input circuit; the preamplifier is configured by bits IGS0-2 of CRD. The total gain must be configured to ensure that a full-scale input signal produces a signal level at the input to the sigma-delta modulator of the ADC that does not exceed the maximum input range. The dc biasing of the analog input signal is accomplished with an on-chip voltage reference. If the input signal is not biased at the internal reference level (via REFOUT), it must be ac-coupled with external coupling capacitors. CIN should be 0.1 F or larger. The dc biasing of the input can then be accomplished using resistors to REFOUT as in Figures 27 through 29.
The AD73411's ADC inputs are biased about the internal reference level (REFCAP level), therefore, it may be necessary to bias external signals to this level using the buffered REFOUT level as the reference. This is applicable in either dc- or ac-coupled configurations. In the case of dc coupling, the signal (biased to REFOUT) may be applied directly to the inputs as shown in Figure 25, or it may be conditioned in an external op amp where it can also be biased to the reference level using the buffered REFOUT signal as shown in Figure 26. In the case of ac-coupling, a capacitor is used to couple the signal to the input of the ADC. The ADC input must be biased to the internal reference (REFCAP) level, which is done by connecting the input to the REFOUT pin through a 10 k resistor as shown in Figure 27.
0.1 F
100 10k 100
VINP
0.047 F
VINN
0.1 F 10k
0/38dB PGA
0.047 F
VREF
VOUTP VOUTN REFOUT
+6/-15dB PGA
CONTINUOUS TIME LOW-PASS FILTER
REFERENCE REFCAP
AD73411
0.1 F
Figure 27. Analog Input (AC-Coupled) Differential
If the ADC is being connected in single-ended mode, the AD73411 should be programmed for single-ended mode using the SEEN and INV bits of CRF, and the inputs connected as shown in Figure 28. When operated in single-ended input mode, the AD73411 can multiplex one of the two inputs to the ADC input, as shown in Figures 28 and 29.
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AD73411
0.1 F 100 10k 0.047 F
VINP
Analog Output
0/38dB PGA
VINN
VREF
VOUTP VOUTN REFOUT REFERENCE REFCAP
+6/-15dB PGA
CONTINUOUS TIME LOW-PASS FILTER
AD73411
0.1 F
The AD73411's differential analog output (VOUT) is produced by an on-chip differential amplifier. The differential output can be ac-coupled or dc-coupled directly to a load that can be a headset or the input of an external amplifier. It is possible to connect the outputs in either a differential or a single-ended configuration, but please note that the effective maximum output voltage swing (peak-to-peak) is halved in the case of single-ended connection. Figure 31 shows a simple circuit providing a differential output with ac coupling. The capacitors in this circuit (COUT) are optional; if used, their value can be chosen as follows:
Figure 28. Analog Input (AC-Coupled) Single-Ended
COUT =
VINP
1 2 fC RLOAD
0.1 F 100 10k 0.047 F
VINN
0/38dB PGA
where fC = desired cutoff frequency.
VINP
VREF
VOUTP VOUTN REFOUT REFERENCE REFCAP
+6/-15dB PGA
CONTINUOUS TIME LOW-PASS FILTER
VINN
COUT
AD73411
RLOAD
VOUTP VOUTN
+6/-15dB PGA
CONTINUOUS TIME LOW-PASS FILTER
0.1 F
COUT
REFOUT REFERENCE
Figure 29. Analog Input (AC-Coupled) Single-Ended (Alternate Input)
Interfacing to an Electret Microphone
AD73411
REFCAP CREFCAP
Figure 30 details an interface for an electret microphone which may be used in some voice applications. Electret microphones typically feature a FET amplifier whose output is accessed on the same lead that supplies power to the microphone; therefore, this output signal must be capacitively coupled to remove the power supply (dc) component. In this circuit the AD73411 input channel is being used in single-ended mode where the inverting amplifier provides suitable gain to scale the input signal relative to the ADC's full-scale input range. The buffered internal reference level at REFOUT is used via an external buffer to provide power to the electret microphone. This provides a quiet, stable supply for the microphone. If this is not a concern, the microphone can be powered from the system power supply.
5V RA 10 F C1 R2 R1
VINP
Figure 31. Example Circuit for Differential Output
Figure 32 shows an example circuit for providing a single-ended output with ac coupling. The capacitor of this circuit (COUT) is not optional if dc current drain is to be avoided.
VINP
VINN
COUT
RLOAD
VOUTP
VOUTN
+6/-15dB PGA
CONTINUOUS TIME LOW-PASS FILTER
REFOUT REFCAP CREFCAP
REFERENCE
AD73411
Figure 32. Example Circuit for Single-Ended Output
RB C2
ELECTRET MICROPHONE
VINN
0/38dB PGA
VREF
VOUTP VOUTN REFOUT REFERENCE REFCAP CREFCAP
+6/-15dB PGA
CONTINUOUS TIME LOW-PASS FILTER
Figure 30. Electret Microphone Interface Circuit
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AD73411
Differential-to-Single-Ended Output
In some applications it may be desirable to convert the full differential output of the decoder channel to a single-ended signal. The circuit of Figure 33 shows a scheme for doing this.
VINP
AFE DIGITAL AFE ANALOG DSP 7 6 5 4 3 2 1
VINN
RF
VOUTP RLOAD
RI
VOUTN
+6/-15dB PGA
RF
RI
REFOUT
CONTINUOUS TIME LOW-PASS FILTER
ABCDE F GH J KLMN PR TU
REFERENCE REFCAP CREFCAP
AD73411
DIGITAL GROUND PLANE ANALOG GROUND PLANE
Figure 33. Example Circuit for Differential-to-SingleEnded Output Conversion
Grounding and Layout
Figure 34. Ground Plane Layout
As the analog inputs to the AD73411's AFE section are differential, most of the voltages in the analog modulator are commonmode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The analog and digital supplies of the AD73411 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. The digital filters on the encoder section will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital filters also remove noise from the analog inputs provided the noise source does not saturate the analog modulator. However, because the resolution of the AD73411's ADC is high, and the noise levels from the AD73411 are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD73411 should be designed so the analog and digital sections are separated and confined to certain sections of the board. The AD73411 ballout configuration offers a major advantage in that its analog interfaces are confined to the last three rows of the package. This facilitates the use of ground planes that can be easily separated, as shown in Figure 34. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place. If this connection is close to the device, it is recommended to use a ferrite bead inductor.
Avoid running digital lines under the AFE section of the device for they will couple noise onto the die. The analog ground plane should be allowed to run under the AD73411's AFE section to avoid noise coupling (see Figure 34). The power supply lines to the AD73411 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply lines. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. Good decoupling is important when using high-speed devices. On the AD73411 both the reference (REFCAP) and supplies need to be decoupled. It is recommended that the decoupling capacitors used on both REFCAP and the supplies, be placed as close as possible to their respective ball connections to ensure high performance from the device. All analog and digital supplies should be decoupled to AGND and DGND respectively, with 0.1 F ceramic capacitors in parallel with 10 F tantalum capacitors. The AFE's digital section supply (DVDD) should be connected to the digital supply that feeds the DSP's VDD(Ext) connections while the AFE's digital ground DGND should be returned to the digital ground plane.
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AD73411
TABLE OF CONTENTS
Topic Page Topic Page
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 POWER CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . 5 TIMING CHARACTERISTICS--AFE SECTION . . . . . . . 5 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PBGA BALL CONFIGURATIONS . . . . . . . . . . . . . . . . . . . 6 PBGA BALL FUNCTION DESCRIPTIONS . . . . . . . . . . . 7 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . 9 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 10 Encoder Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . 10 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 10 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Analog Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . 11 Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ADC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Decoder Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DAC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Analog Smoothing Filter and PGA . . . . . . . . . . . . . . . . . 12 Differential Output Amplifiers . . . . . . . . . . . . . . . . . . . . . 12 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AFE Serial Port (SPORT2) . . . . . . . . . . . . . . . . . . . . . . . 12 SPORT2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPORT2 Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 13 Sample Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DAC Advance Register . . . . . . . . . . . . . . . . . . . . . . . . . . 14 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Resetting the AFE Section of the AD73411 . . . . . . . . . . . 14 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AFE Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program (Control) Mode . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mixed Program/Data Mode . . . . . . . . . . . . . . . . . . . . . . . 18 Digital Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Sport Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Analog Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AFE Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FUNCTIONAL DESCRIPTION--DSP . . . . . . . . . . . . . . 21 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DSP SECTION PIN DESCRIPTIONS . . . . . . . . . . . . . . . 22 Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Terminating Unused Pin . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LOW-POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 24 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . 25 Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . 26 PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program Memory (Full Memory Mode) . . . . . . . . . . . . . 26 Program Memory (Host Mode) . . . . . . . . . . . . . . . . . . . . 26 DATA MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Data Memory (Full Memory Mode) . . . . . . . . . . . . . . . . 26 I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . . 27 Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . . 27 Boot Memory Select (BMS) Disable . . . . . . . . . . . . . . . . 27 Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Byte Memory DMA (BDMA, Full Memory Mode) . . . . . 27 Internal Memory DMA Port (IDMA Port; Host Memory Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . . 29 IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bus Request and Bus Grant (Full Memory Mode) . . . . . . 29 Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 INSTRUCTION SET DESCRIPTION . . . . . . . . . . . . . . . 29 DESIGNING AN EZ-ICE(R)-COMPATIBLE SYSTEM . . . 29 Target Board Connector for EZ-ICE Probe . . . . . . . . . . . 30 Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 30 PM, DM, BM, IOM, and CM . . . . . . . . . . . . . . . . . . . . . 30 Target Systems Interface Signals . . . . . . . . . . . . . . . . . . . 30 ANALOG FRONT END (AFE) INTERFACING . . . . . . . 31 DSP SPORT to AFE Interfacing . . . . . . . . . . . . . . . . . . . 31 Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Interfacing to the AFE's Analog Inputs and Outputs . . . . 31 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Interfacing to an Electret Microphone . . . . . . . . . . . . . . . 33 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Differential-to-Single-Ended Output . . . . . . . . . . . . . . . . 34 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 36
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AD73411
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
119-Ball Plastic Ball Grid Array (PBGA) B-119
0.559 (14.20) 0.543 (13.80) 0.300 (7.62) BSC BOTTOM VIEW
7654321
A1
TOP VIEW
0.874 (22.20) 0.858 (21.80)
0.050 (1.27) BSC
0.033 (0.84) REF 0.126 (3.19) REF DETAIL A 0.089 (2.27) 0.073 (1.85) 0.028 (0.70) 0.020 (0.50) 0.050 (1.27) BSC
A B C D E F G H J K L M N P R T U
0.800 (20.32) BSC
DETAIL A
0.037 (0.95) 0.033 (0.85)
SEATING PLANE
0.035 (0.90) 0.024 (0.60) BALL DIAMETER
0.022 (0.56) REF
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PRINTED IN U.S.A.
C01031-5-7/00 (rev. 0)

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